Framework Partnership Agreement (FPA) for developing a large-scale European initiative for High Performance Computing (HPC) ecosystem based on RISC-V -

Expected Outcome:

Framework Programme Agreement (FPA) for European hardware and software technologies, based on RISC-V in order to deliver high-end processors and/or accelerators and systems based on a strategic research roadmap, and the realisation of test-beds, pilots and/or demonstrators, integrating these processors.

The FPA is expected to address the following outcomes:

• Contribution towards European technological sovereignty, by establishing, maintaining and implementing a strategic R&I roadmap that fosters the European capabilities to design, develop and produce the IP related to high-end processors and/or accelerators based on RISC-V, driven by relevant key performance indicators.
• Designing and delivering energy efficient high-end processors and accelerators for HPC based on RISC-V hardware solutions, test-beds, and at least one pilot integrating these processors/accelerators. The development of European processors and/or accelerators should prepare the technology for its future integration in post-exascale supercomputers to be acquired at a later stage by the EuroHPC JU targeting systems incorporating European technologies.
• A suitable software stack, including key elements such as programming models and runtimes (e.g. languages, compilers, programming environments, communication), libraries (e.g. mathematical, data analytics, AI frameworks), tools (e.g. debuggers, performance, system monitoring), operating system components (e.g. schedulers, workflows, software management, security), and other elements (e.g. for networking, software deployment, system-level composability and modularity of software, etc.).
• The necessary components adapted for the integration of the RISC-V based components in industrial grade HPC or Cloud solutions.
• A selected set of critical HPC applications, encompassing amongst others the major EuroHPC use-cases, ported and optimised to the new RISC-V based environment, based on a co-design approach.
• Standards and interface specifications for the software and hardware stack, with clear definition of standardization and licensing schemes of the developed Intellectual Property (IP), with mechanism to guarantee that this IP remains in the EU.
• Reinforce the use of pilot lines based in Europe and, widen the skill base for the design and manufacturing of high-end components.
• A long-term roadmap with a critical timeline, milestones and all the necessary activities that would be needed to build and deploy post-exascale systems in Europe using European technology.

Scope:

The aim is to support a Framework Partnership Agreement (FPA) establishing a stable and structured long term partnership between the EuroHPC JU and a consortium of industry, research organisations and the institutions in High Performance Computing who commit themselves to establishing, coordinating and implementing a strategic and ambitious R&I initiative contributing to the development of innovative HPC hardware and software technology based on the open RISC-V ecosystem, followed by an ambitious action for building and deploying the exascale and post-exascale supercomputers based on this technology.

This partnership will be set up through one single FPA, which will ensure the implementation of the initiative through several complementary parallel and consecutive Specific Grant Agreements (SGAs) that will carry out the different activities in a common framework. The SGAs will be implemented as Research and Innovation Actions (RIA) or Innovation Actions (IA) in function of the concrete objectives of the action. The FPA should be carried out in different phases, which will be triggered after the attainment of appropriate intermediate progress milestones identified by the Consortium. The FPA will permit the coordinated development of the technology, its validation and the nurturing of the ecosystem. The developments should be integrated in at least one pilot demonstrator to validate the developments and demonstrate the scalability potential towards exascale systems. The demonstrator should be installed in a pre-operational environment in European supercomputing centres for user testing and validation. The FPA and its SGAs should target delivering of technological components for building and deploying in the EU exascale and post-exascale supercomputers based on European technology.

The FPA is expected to pursue an inclusive approach in the development of the necessary EU-wide RISC V ecosystem, ensuring European wide participation of relevant stakeholders across the EU and take-up of the technology developed. The FPA should include supercomputing centres, research institutes, universities, RTOs, industry, SMEs as well as any other organisations that can play a role in the realisation of the objectives of the initiative. The participation of the leading supercomputing centres in Europe is essential to provide upfront the general specifications of the future European supercomputers to ensure the proper alignment of the technological developments to the needs of the users. In addition, the FPA should aim towards a strong participation of the European HPC supplier as well as server/cloud supplier industry, including SMEs, so that they can leverage on existing technological developments and activities and, reinforce their capabilities of becoming leading technology suppliers.

The FPA should ensure a common framework for implementation by maintaining a long-term roadmap with a critical timeline and milestones of the necessary activities (including also other related activities funded outside EuroHPC) that would be needed to build and deploy exascale and post-exascale systems in Europe using the technology developed in this initiative.

Proposals for FPAs should present an overall view of the different main areas of work to be implemented by SGAs, addressing them in a co-design approach. The co-design approach should bridge the gap between suppliers and users; define the characteristics and technical features of the new hardware architectures and where necessary the additional key components, existing or to be developed; as well as better computational methods and algorithms adapted to future real HPC application needs with a minimum significative number of use cases that demonstrate the capability of the developed solutions for solving concrete and challenging computational problems demonstrating a competitive edge in application areas that are crucial for the Union. The FPA should address in a co-design approach at least the topics listed below:

RISC-V hardware: addressing the design, development, testing, tape-out of different generations of energy efficient high-end processors and/or accelerators, in particular chiplet-based approaches, for High Performance Computing (HPC), also linked to cloud or data server use cases, using synergies with designs and components developed by projects funded through the Key Digital Technologies Joint Undertaking resp. Chips Joint Undertaking where relevant,

Integration in test-beds and at least one pilot in pre-operational environments in supercomputing centres for user testing and validation.

RISC-V software: develop the full SW stack and the associated software ecosystem for the developed processors and/or accelerators, addressing the system, middleware and application layers. The development should be driven by the needs of relevant HPC workflows and application requirements and cloud or data server use cases where relevant.

Develop and/or adapt the other necessary technologies for the integration of the RISC-V based components into industrial grade HPC solutions.

Identify the most critical HPC applications and domains and work towards porting and optimising them for the new RISC-V based environment, and the wide take-up of the developed technology by users.

Explore and exploit existing manufacturing capabilities in Europe, including existing or under development pilot lines, to fabricate the required components.

The FPA should develop mechanisms guaranteeing that all IP generated in the initiative stays in the EU and will not be transferred to third countries, dedicating an appropriate effort to IP management, protection and exploitation (i.e., IP licensing, IP warranty, etc.).

The FPA should present a professional project structure management, a strategic R&I roadmap to implement the activities, and governance that are appropriate to coordinate the implementation of the future SGAs, including addressing the industrial use cases, and to deliver effectively and efficiently the main results of the initiative. The FPA should put in place appropriate management and progress control mechanisms, in particular, the establishment of common milestones for the SGAs and an intermediate main assessment point to assess the correct advancement of the different work lines towards the goals of the overall initiative.

The FPA should establish interaction with the relevant stakeholders and Programs of the KDT/Chips JU to coordinate work on horizontal issues common to both communities and exploit synergies where relevant, in particular for pilot lines for high end components, common design rules and tools.

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